1. Field of the Invention
The invention relates to integrated circuits and more particularly relates to circuit configurations and operations that mitigate the effects of charge sharing.
2. Background
Advances in semiconductor manufacturing technologies have allowed circuit designers to integrate tremendous numbers of transistors on a single die. For example, modern integrated circuits (ICs) commonly include several million transistors interconnected on a single, small substrate. Typically, these are field effect transistors (FETs). At the same time, computer architecture, and more particularly processor architecture, has gone in the direction of emphasizing shorter and shorter cycle times. These advances in semiconductor manufacturing and processor architecture have led designers to consider new ways of implementing basic circuit functions.
Producing integrated circuits with shorter cycle times, means increasing the clock frequency at which these devices operate. Increasing clock frequencies means that fewer logic gate delays are permitted within each clock cycle. Several styles of logic design have been developed to achieve high speed operation. Among these are domino logic circuits.
Domino circuits implemented with complementary metal oxide semiconductor (CMOS) FET configurations provide high speed operation by, among other things, reducing the amount of parasitic junction capacitance at their output nodes as compared to conventional fully static logic implementations of complex logic functions. Unfortunately, such domino circuits have traditionally suffered from noise induced by charge sharing.
What is needed are circuits and methods for providing charge sharing protection for domino circuits.